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Searched refs:regDTBCLK_DTO3_PHASE (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h212 #define regDTBCLK_DTO3_PHASE … macro
H A Ddcn_3_1_5_offset.h206 #define regDTBCLK_DTO3_PHASE … macro
H A Ddcn_3_5_1_offset.h1347 #define regDTBCLK_DTO3_PHASE … macro
H A Ddcn_3_5_0_offset.h1368 #define regDTBCLK_DTO3_PHASE … macro
H A Ddcn_3_1_4_offset.h1509 #define regDTBCLK_DTO3_PHASE … macro
H A Ddcn_3_1_2_offset.h417 #define regDTBCLK_DTO3_PHASE … macro
H A Ddcn_3_2_1_offset.h212 #define regDTBCLK_DTO3_PHASE … macro
H A Ddcn_3_1_6_offset.h619 #define regDTBCLK_DTO3_PHASE … macro