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Searched refs:regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4466 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h5605 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5735 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5756 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6755 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h5846 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4465 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6066 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4897 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro