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Searched refs:regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4074 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4911 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5321 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5342 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6061 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h5152 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4073 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h5372 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4386 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … macro