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Searched refs:regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h3354 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h3587 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4557 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4578 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h4737 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h3828 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3353 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4048 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3427 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … macro