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Searched refs:regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h12118 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10922 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10943 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12045 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h12108 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h12396 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX … macro