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Searched refs:regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h11866 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12505 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10642 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10663 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11765 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12640 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11869 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13236 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h12092 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX … macro