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Searched refs:regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h11842 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12481 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10618 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10639 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11741 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12616 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11845 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13212 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h12068 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX … macro