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Searched refs:regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h11795 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro
H A Ddcn_3_1_5_offset.h12420 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro
H A Ddcn_3_5_1_offset.h10558 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro
H A Ddcn_3_5_0_offset.h10579 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro
H A Ddcn_3_1_4_offset.h11680 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro
H A Ddcn_3_1_2_offset.h12555 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro
H A Ddcn_3_2_1_offset.h11804 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro
H A Ddcn_3_1_6_offset.h13151 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL … macro