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Searched refs:regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h11734 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12359 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10497 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10518 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11619 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12494 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11743 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13090 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h11934 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX … macro