Home
last modified time | relevance | path

Searched refs:regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h11754 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12379 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10517 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10538 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11639 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12514 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11763 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13110 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h11928 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX … macro