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Searched refs:regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h11770 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12395 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10533 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10554 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11655 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12530 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h11779 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13126 #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro