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Searched refs:regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h10078 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h10665 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h9687 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h9708 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h10829 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h10910 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h10077 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h11134 #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … macro