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Searched refs:regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h8960 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h9595 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h8209 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h8230 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h9415 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h9840 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8959 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h10064 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h9630 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … macro