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Searched refs:regDME5_DME_MEMORY_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h12252 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12821 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h13286 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h13307 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12423 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12958 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h12236 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13554 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h13005 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX … macro