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Searched refs:regDEV0_PF1_D3HOTD0_RST_CTRL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h5698 #define regDEV0_PF1_D3HOTD0_RST_CTRL … macro
H A Dnbio_4_3_0_offset.h13646 #define regDEV0_PF1_D3HOTD0_RST_CTRL … macro
H A Dnbio_7_7_0_offset.h6836 #define regDEV0_PF1_D3HOTD0_RST_CTRL … macro
H A Dnbio_7_2_0_offset.h7594 #define regDEV0_PF1_D3HOTD0_RST_CTRL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_3_1_offset.h7313 #define regDEV0_PF1_D3HOTD0_RST_CTRL … macro