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Searched refs:regDCIO_GSL_GENLK_PAD_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h6262 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddpcs_4_2_3_offset.h635 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddpcs_4_2_2_offset.h599 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddpcs_4_2_0_offset.h602 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h10961 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_3_1_5_offset.h11556 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_3_5_1_offset.h9788 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_3_5_0_offset.h9809 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_3_1_4_offset.h10920 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_3_1_2_offset.h11811 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_3_2_1_offset.h10970 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_3_1_6_offset.h12047 #define regDCIO_GSL_GENLK_PAD_CNTL … macro
H A Ddcn_4_1_0_offset.h11223 #define regDCIO_GSL_GENLK_PAD_CNTL … macro