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Searched refs:regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h185 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h179 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h1322 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h1343 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h1484 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h392 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h185 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h592 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h207 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro