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Searched refs:regDAGB1_CNTL_MISC2 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v4_1_0.c545 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); in mmhub_v4_1_0_update_medium_grain_clock_gating()
575 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); in mmhub_v4_1_0_update_medium_grain_clock_gating()
H A Dmmhub_v3_0.c549 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); in mmhub_v3_0_update_medium_grain_clock_gating()
595 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); in mmhub_v3_0_update_medium_grain_clock_gating()
H A Dmmhub_v4_2_0.c834 def2 = data2 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2); in mmhub_v4_2_0_update_medium_grain_clock_gating()
858 WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2, data2); in mmhub_v4_2_0_update_medium_grain_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_4_1_0_offset.h486 #define regDAGB1_CNTL_MISC2 … macro
H A Dmmhub_3_0_2_offset.h510 #define regDAGB1_CNTL_MISC2 … macro
H A Dmmhub_3_0_0_offset.h508 #define regDAGB1_CNTL_MISC2 … macro
H A Dmmhub_1_8_0_offset.h506 #define regDAGB1_CNTL_MISC2 … macro
H A Dmmhub_1_7_offset.h502 #define regDAGB1_CNTL_MISC2 … macro