Searched refs:regCP_RB_DOORBELL_CONTROL (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v12_0.c | 2550 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v12_0_cp_gfx_resume()
2560 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v12_0_cp_gfx_resume()
2899 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v12_0_cp_async_gfx_ring_resume()
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| H A D | gfx_v11_0.c | 3509 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_cp_gfx_resume()
3519 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v11_0_cp_gfx_resume()
3967 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_cp_async_gfx_ring_resume()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 2856 #define regCP_RB_DOORBELL_CONTROL … macro
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| H A D | gc_9_4_2_offset.h | 403 #define regCP_RB_DOORBELL_CONTROL … macro
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| H A D | gc_11_5_0_offset.h | 3399 #define regCP_RB_DOORBELL_CONTROL … macro
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| H A D | gc_12_0_0_offset.h | 3706 #define regCP_RB_DOORBELL_CONTROL … macro
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| H A D | gc_11_0_3_offset.h | 4650 #define regCP_RB_DOORBELL_CONTROL … macro
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| H A D | gc_11_0_0_offset.h | 4426 #define regCP_RB_DOORBELL_CONTROL … macro
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