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Searched refs:regCP_RB1_WPTR (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c127 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
3658 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2850 #define regCP_RB1_WPTR … macro
H A Dgc_9_4_2_offset.h397 #define regCP_RB1_WPTR … macro
H A Dgc_11_5_0_offset.h3151 #define regCP_RB1_WPTR … macro
H A Dgc_11_0_3_offset.h4388 #define regCP_RB1_WPTR … macro
H A Dgc_11_0_0_offset.h4170 #define regCP_RB1_WPTR … macro