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Searched refs:regCP_RB1_BASE (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c125 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
3675 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2870 #define regCP_RB1_BASE … macro
H A Dgc_9_4_2_offset.h417 #define regCP_RB1_BASE … macro
H A Dgc_11_5_0_offset.h3169 #define regCP_RB1_BASE … macro
H A Dgc_11_0_3_offset.h4406 #define regCP_RB1_BASE … macro
H A Dgc_11_0_0_offset.h4188 #define regCP_RB1_BASE … macro