Searched refs:regCP_RB0_WPTR_HI (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v12_0.c | 2644 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v12_0_cp_gfx_resume()
4207 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v12_0_ring_get_wptr_gfx()
4252 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v12_0_ring_set_wptr_gfx()
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| H A D | gfx_v11_0.c | 3620 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
5588 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v11_0_ring_get_wptr_gfx()
5606 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v11_0_ring_set_wptr_gfx()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 2846 #define regCP_RB0_WPTR_HI … macro
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| H A D | gc_9_4_2_offset.h | 393 #define regCP_RB0_WPTR_HI … macro
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| H A D | gc_11_5_0_offset.h | 3147 #define regCP_RB0_WPTR_HI … macro
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| H A D | gc_12_0_0_offset.h | 3506 #define regCP_RB0_WPTR_HI … macro
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| H A D | gc_11_0_3_offset.h | 4384 #define regCP_RB0_WPTR_HI … macro
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| H A D | gc_11_0_0_offset.h | 4166 #define regCP_RB0_WPTR_HI … macro
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