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Searched refs:regCP_RB0_WPTR_HI (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c2736 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v12_0_cp_gfx_resume()
4330 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v12_0_ring_get_wptr_gfx()
4348 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v12_0_ring_set_wptr_gfx()
H A Dgfx_v11_0.c3740 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
5775 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v11_0_ring_get_wptr_gfx()
5793 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v11_0_ring_set_wptr_gfx()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2846 #define regCP_RB0_WPTR_HI … macro
H A Dgc_9_4_2_offset.h393 #define regCP_RB0_WPTR_HI … macro
H A Dgc_12_0_0_offset.h3506 #define regCP_RB0_WPTR_HI … macro
H A Dgc_11_0_3_offset.h4384 #define regCP_RB0_WPTR_HI … macro
H A Dgc_11_0_0_offset.h4166 #define regCP_RB0_WPTR_HI … macro