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Searched refs:regCP_RB0_WPTR (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
2774 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v12_0_cp_gfx_resume()
4447 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v12_0_ring_get_wptr_gfx()
4464 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v12_0_ring_set_wptr_gfx()
H A Dgfx_v11_0.c167 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
3815 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
5931 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v11_0_ring_get_wptr_gfx()
5948 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
H A Dgfx_v12_1.c95 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2842 #define regCP_RB0_WPTR … macro
H A Dgc_9_4_2_offset.h389 #define regCP_RB0_WPTR … macro
H A Dgc_12_0_0_offset.h3502 #define regCP_RB0_WPTR … macro
H A Dgc_11_0_3_offset.h4380 #define regCP_RB0_WPTR … macro
H A Dgc_11_0_0_offset.h4162 #define regCP_RB0_WPTR … macro