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Searched refs:regCP_RB0_BASE (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
2760 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); in gfx_v12_0_cp_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2784 #define regCP_RB0_BASE … macro
H A Dgc_9_4_2_offset.h333 #define regCP_RB0_BASE … macro
H A Dgc_12_0_0_offset.h3456 #define regCP_RB0_BASE … macro
H A Dgc_11_0_3_offset.h4330 #define regCP_RB0_BASE … macro
H A Dgc_11_0_0_offset.h4114 #define regCP_RB0_BASE … macro