Searched refs:regCP_PFP_IC_OP_CNTL (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v11_0.c | 2419 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2421 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2425 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2527 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2540 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2542 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2545 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
3137 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3150 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3152 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
[all …]
|
| H A D | gfx_v12_0.c | 2328 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2341 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2343 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2346 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_11_5_0_offset.h | 8397 #define regCP_PFP_IC_OP_CNTL … macro
|
| H A D | gc_12_0_0_offset.h | 6202 #define regCP_PFP_IC_OP_CNTL … macro
|
| H A D | gc_11_0_3_offset.h | 10276 #define regCP_PFP_IC_OP_CNTL … macro
|
| H A D | gc_11_0_0_offset.h | 9726 #define regCP_PFP_IC_OP_CNTL … macro
|