Searched refs:regCP_PFP_IC_OP_CNTL (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v11_0.c | 2355 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2357 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2361 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2463 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2476 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2478 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2481 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
3073 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3086 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3088 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tm in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
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| H A D | gfx_v12_0.c | 2282 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2295 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2297 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2300 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_11_5_0_offset.h | 8397 #define regCP_PFP_IC_OP_CNTL … macro
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| H A D | gc_12_0_0_offset.h | 6202 #define regCP_PFP_IC_OP_CNTL … macro
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| H A D | gc_11_0_3_offset.h | 10276 #define regCP_PFP_IC_OP_CNTL … macro
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| H A D | gc_11_0_0_offset.h | 9726 #define regCP_PFP_IC_OP_CNTL … macro
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