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Searched refs:regCP_ME_PRGRM_CNTR_START (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2683 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_me_cache_rs64()
2867 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
3389 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
H A Dgfx_v12_0.c2049 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v12_0_config_gfx_rs64()
2147 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v12_0_set_me_ucode_start_addr()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3002 #define regCP_ME_PRGRM_CNTR_START macro
H A Dgc_9_4_2_offset.h541 #define regCP_ME_PRGRM_CNTR_START macro
H A Dgc_11_5_0_offset.h3263 #define regCP_ME_PRGRM_CNTR_START macro
H A Dgc_12_0_0_offset.h3580 #define regCP_ME_PRGRM_CNTR_START macro
H A Dgc_11_0_3_offset.h4514 #define regCP_ME_PRGRM_CNTR_START macro
H A Dgc_11_0_0_offset.h4290 #define regCP_ME_PRGRM_CNTR_START macro