Searched refs:regCP_ME_IC_OP_CNTL (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v11_0.c | 2366 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2368 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2372 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2640 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2653 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2655 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2659 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
3346 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3359 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3361 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
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| H A D | gfx_v12_0.c | 2448 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2461 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2463 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2467 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_11_5_0_offset.h | 8405 #define regCP_ME_IC_OP_CNTL … macro
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| H A D | gc_12_0_0_offset.h | 6210 #define regCP_ME_IC_OP_CNTL … macro
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| H A D | gc_11_0_3_offset.h | 10284 #define regCP_ME_IC_OP_CNTL … macro
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| H A D | gc_11_0_0_offset.h | 9734 #define regCP_ME_IC_OP_CNTL … macro
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