Home
last modified time | relevance | path

Searched refs:regCP_ME_IC_BASE_HI (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2525 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache()
2753 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache_rs64()
3460 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
H A Dgfx_v12_0.c2550 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h6206 #define regCP_ME_IC_BASE_HI … macro
H A Dgc_11_0_3_offset.h10280 #define regCP_ME_IC_BASE_HI … macro
H A Dgc_11_0_0_offset.h9730 #define regCP_ME_IC_BASE_HI … macro