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Searched refs:regCP_ME_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2720 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2727 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2736 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2843 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2850 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2859 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
3004 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
3007 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3012 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3026 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
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H A Dgfx_v12_0.c2142 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2145 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2150 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2164 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2167 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2172 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2221 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_pfp_ucode_start_addr()
2228 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2237 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2263 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_me_ucode_start_addr()
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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h196 #define regCP_ME_CNTL macro
H A Dgc_9_4_2_offset.h239 #define regCP_ME_CNTL macro
H A Dgc_12_0_0_offset.h4058 #define regCP_ME_CNTL macro
H A Dgc_11_0_3_offset.h6478 #define regCP_ME_CNTL macro
H A Dgc_11_0_0_offset.h6198 #define regCP_ME_CNTL macro