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Searched refs:regCP_ME_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2761 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2768 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2777 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2884 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2891 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2900 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
3045 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
3048 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3053 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3067 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
[all …]
H A Dgfx_v12_0.c2168 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2171 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2176 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2190 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_config_gfx_rs64()
2193 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2198 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2247 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_pfp_ucode_start_addr()
2254 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2263 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2289 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v12_0_set_me_ucode_start_addr()
[all …]
H A Dmes_v11_0.c451 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); in mes_v11_0_reset_gfx_pipe_mmio()
452 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); in mes_v11_0_reset_gfx_pipe_mmio()
H A Dmes_v12_0.c466 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); in mes_v12_0_reset_gfx_pipe_mmio()
467 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); in mes_v12_0_reset_gfx_pipe_mmio()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h196 #define regCP_ME_CNTL … macro
H A Dgc_9_4_2_offset.h239 #define regCP_ME_CNTL … macro
H A Dgc_12_0_0_offset.h4058 #define regCP_ME_CNTL … macro
H A Dgc_11_0_3_offset.h6478 #define regCP_ME_CNTL … macro
H A Dgc_11_0_0_offset.h6198 #define regCP_ME_CNTL … macro