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Searched refs:regCP_MES_IC_BASE_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_0.c946 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); in mes_v12_0_load_microcode()
H A Dmes_v11_0.c1010 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); in mes_v11_0_load_microcode()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h8421 #define regCP_MES_IC_BASE_CNTL … macro
H A Dgc_12_0_0_offset.h6226 #define regCP_MES_IC_BASE_CNTL … macro
H A Dgc_11_0_3_offset.h10300 #define regCP_MES_IC_BASE_CNTL … macro
H A Dgc_11_0_0_offset.h9750 #define regCP_MES_IC_BASE_CNTL … macro