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Searched refs:regCP_MES_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c965 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
969 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
992 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
999 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
1008 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
H A Dmes_v12_0.c1112 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v12_0_enable()
1117 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
1131 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
1144 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v12_0_enable()
1152 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
H A Dgfx_v12_0.c131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4634 #define regCP_MES_CNTL … macro
H A Dgc_11_0_3_offset.h7750 #define regCP_MES_CNTL … macro
H A Dgc_11_0_0_offset.h7444 #define regCP_MES_CNTL … macro