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Searched refs:regCP_MES_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_0.c854 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v12_0_enable()
857 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
875 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
884 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v12_0_enable()
892 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
H A Dmes_v11_0.c936 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
940 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
963 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
970 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
979 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
H A Dgfx_v12_0.c112 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
H A Dgfx_v11_0.c153 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h6219 #define regCP_MES_CNTL … macro
H A Dgc_12_0_0_offset.h4634 #define regCP_MES_CNTL … macro
H A Dgc_11_0_3_offset.h7750 #define regCP_MES_CNTL … macro
H A Dgc_11_0_0_offset.h7444 #define regCP_MES_CNTL … macro