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Searched refs:regCP_MEC_RS64_PRGRM_CNTR_START (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_1.c1797 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v12_1_xcc_config_gfx_rs64()
1842 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v12_1_xcc_set_mec_ucode_start_addr()
H A Dgfx_v11_0.c2924 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_mec_cache_rs64()
3039 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
4019 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v12_0.c2177 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v12_0_config_gfx_rs64()
2295 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v12_0_set_mec_ucode_start_addr()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4946 #define regCP_MEC_RS64_PRGRM_CNTR_START … macro
H A Dgc_11_0_3_offset.h8058 #define regCP_MEC_RS64_PRGRM_CNTR_START … macro
H A Dgc_11_0_0_offset.h7754 #define regCP_MEC_RS64_PRGRM_CNTR_START … macro