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Searched refs:regCP_MEC_RS64_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c2034 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_set_pfp_ucode_start_addr()
2039 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_set_pfp_ucode_start_addr()
2046 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_set_me_ucode_start_addr()
2644 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2665 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v12_0_cp_compute_load_microcode_rs64()
H A Dgfx_v11_0.c2834 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_wait_for_rlc_autoload_complete()
2839 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_wait_for_rlc_autoload_complete()
2846 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_wait_for_rlc_autoload_complete()
3634 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_load_microcode()
3655 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_load_microcode_rs64()
4884 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_get_gpu_clock_counter()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h6535 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_12_0_0_offset.h4952 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_3_offset.h8066 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_0_offset.h7762 #define regCP_MEC_RS64_CNTL … macro