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Searched refs:regCP_MEC_RS64_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c2173 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_config_gfx_rs64()
2178 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2185 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2776 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_cp_compute_enable()
2797 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v12_0_cp_compute_enable()
5343 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_reset_compute_pipe()
5375 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); in gfx_v12_0_reset_compute_pipe()
5376 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); in gfx_v12_0_reset_compute_pipe()
H A Dgfx_v11_0.c3017 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
3022 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3029 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3818 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3839 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
5103 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
6871 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_reset_compute_pipe()
6904 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); in gfx_v11_0_reset_compute_pipe()
6905 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); in gfx_v11_0_reset_compute_pipe()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4952 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_3_offset.h8066 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_0_offset.h7762 #define regCP_MEC_RS64_CNTL … macro