Home
last modified time | relevance | path

Searched refs:regCP_MEC_RS64_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c498 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in mes_v11_0_reset_compute_pipe_mmio()
529 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); in mes_v11_0_reset_compute_pipe_mmio()
531 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); in mes_v11_0_reset_compute_pipe_mmio()
H A Dmes_v12_0.c513 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in mes_v12_0_reset_compute_pipe_mmio()
544 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); in mes_v12_0_reset_compute_pipe_mmio()
547 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); in mes_v12_0_reset_compute_pipe_mmio()
H A Dgfx_v12_1.c2124 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); in gfx_v12_1_xcc_config_gfx_rs64()
2129 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); in gfx_v12_1_xcc_config_gfx_rs64()
2136 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); in gfx_v12_1_xcc_config_gfx_rs64()
2220 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); in gfx_v12_1_xcc_cp_compute_enable()
2241 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data); in gfx_v12_1_xcc_cp_compute_enable()
H A Dgfx_v12_0.c2212 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_config_gfx_rs64()
2217 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2224 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2815 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_cp_compute_enable()
2836 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v12_0_cp_compute_enable()
H A Dgfx_v11_0.c3089 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
3094 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3101 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3894 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3915 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
5270 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4952 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_3_offset.h8066 #define regCP_MEC_RS64_CNTL … macro
H A Dgc_11_0_0_offset.h7762 #define regCP_MEC_RS64_CNTL … macro