Home
last modified time | relevance | path

Searched refs:regCP_MEC_DC_BASE_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2880 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2883 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
3974 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3977 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v12_0.c2869 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2872 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4966 #define regCP_MEC_DC_BASE_CNTL … macro
H A Dgc_11_0_3_offset.h8080 #define regCP_MEC_DC_BASE_CNTL … macro
H A Dgc_11_0_0_offset.h7776 #define regCP_MEC_DC_BASE_CNTL … macro