Searched refs:regCP_ME1_PIPE1_INT_CNTL (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_4_3.c | 3107 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3157 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); in gfx_v9_4_3_get_cpc_int_cntl()
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| H A D | gfx_v12_0.c | 1771 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_get_cpc_int_cntl()
4726 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
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| H A D | gfx_v11_0.c | 2076 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
6229 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 2942 #define regCP_ME1_PIPE1_INT_CNTL … macro
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| H A D | gc_9_4_2_offset.h | 481 #define regCP_ME1_PIPE1_INT_CNTL … macro
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| H A D | gc_11_5_0_offset.h | 3207 #define regCP_ME1_PIPE1_INT_CNTL … macro
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| H A D | gc_12_0_0_offset.h | 3560 #define regCP_ME1_PIPE1_INT_CNTL … macro
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| H A D | gc_11_0_3_offset.h | 4454 #define regCP_ME1_PIPE1_INT_CNTL … macro
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| H A D | gc_11_0_0_offset.h | 4234 #define regCP_ME1_PIPE1_INT_CNTL … macro
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