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Searched refs:regCP_ME1_PIPE1_INT_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c1877 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_get_cpc_int_cntl()
4789 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
H A Dgfx_v11_0.c2226 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
6445 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
H A Dgfx_v12_1.c3557 regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2942 #define regCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_9_4_2_offset.h481 #define regCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_12_0_0_offset.h3560 #define regCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_11_0_3_offset.h4454 #define regCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_11_0_0_offset.h4234 #define regCP_ME1_PIPE1_INT_CNTL … macro