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Searched refs:regCP_ME1_PIPE0_INT_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3183 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3234 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); in gfx_v9_4_3_get_cpc_int_cntl()
H A Dgfx_v12_1.c3901 regCP_ME1_PIPE0_INT_CNTL); in gfx_v12_1_xcc_set_compute_eop_interrupt_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2940 #define regCP_ME1_PIPE0_INT_CNTL … macro
H A Dgc_9_4_2_offset.h479 #define regCP_ME1_PIPE0_INT_CNTL … macro
H A Dgc_12_0_0_offset.h3558 #define regCP_ME1_PIPE0_INT_CNTL … macro
H A Dgc_11_0_3_offset.h4452 #define regCP_ME1_PIPE0_INT_CNTL … macro
H A Dgc_11_0_0_offset.h4232 #define regCP_ME1_PIPE0_INT_CNTL … macro