Home
last modified time | relevance | path

Searched refs:regCP_INT_CNTL_RING0 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_1.c1505 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); in gfx_v12_1_xcc_enable_gui_idle_interrupt()
1516 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); in gfx_v12_1_xcc_enable_gui_idle_interrupt()
H A Dgfx_v12_0.c1856 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v12_0_get_cpg_int_cntl()
4738 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v12_0_set_gfx_eop_interrupt_state()
H A Dgfx_v11_0.c2203 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_get_cpg_int_cntl()
6391 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2890 #define regCP_INT_CNTL_RING0 … macro
H A Dgc_9_4_2_offset.h437 #define regCP_INT_CNTL_RING0 … macro
H A Dgc_12_0_0_offset.h3528 #define regCP_INT_CNTL_RING0 … macro
H A Dgc_11_0_3_offset.h4416 #define regCP_INT_CNTL_RING0 … macro
H A Dgc_11_0_0_offset.h4198 #define regCP_INT_CNTL_RING0 … macro