Home
last modified time | relevance | path

Searched refs:regCP_INT_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c4786 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4791 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4896 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_ring_emit_gds_switch()
4901 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_ring_emit_gds_switch()
5239 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_update_gfx_clock_gating()
5244 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v11_0_update_spm_vmid()
H A Dgfx_v12_0.c3936 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v12_0_update_medium_grain_clock_gating()
3941 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v12_0_update_medium_grain_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2812 #define regCP_INT_CNTL … macro
H A Dgc_9_4_2_offset.h359 #define regCP_INT_CNTL … macro
H A Dgc_11_5_0_offset.h3117 #define regCP_INT_CNTL … macro
H A Dgc_12_0_0_offset.h3482 #define regCP_INT_CNTL … macro
H A Dgc_11_0_3_offset.h4354 #define regCP_INT_CNTL … macro
H A Dgc_11_0_0_offset.h4136 #define regCP_INT_CNTL … macro