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Searched refs:regCP_HQD_WG_STATE_OFFSET (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3382 #define regCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_9_4_2_offset.h793 #define regCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_12_0_0_offset.h3940 #define regCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_11_0_3_offset.h4924 #define regCP_HQD_WG_STATE_OFFSET … macro
H A Dgc_11_0_0_offset.h4700 #define regCP_HQD_WG_STATE_OFFSET … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
H A Dgfx_v11_0.c230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),