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Searched refs:regCP_HQD_PQ_RPTR_REPORT_ADDR (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_0.c1142 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in mes_v12_0_queue_init_register()
H A Dmes_v11_0.c1169 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in mes_v11_0_queue_init_register()
H A Dgfx_v9_4_3.c1987 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v12_0.c3185 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c4241 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v11_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3304 #define regCP_HQD_PQ_RPTR_REPORT_ADDR macro
H A Dgc_9_4_2_offset.h715 #define regCP_HQD_PQ_RPTR_REPORT_ADDR macro
H A Dgc_11_5_0_offset.h3595 #define regCP_HQD_PQ_RPTR_REPORT_ADDR macro
H A Dgc_12_0_0_offset.h3864 #define regCP_HQD_PQ_RPTR_REPORT_ADDR macro
H A Dgc_11_0_3_offset.h4846 #define regCP_HQD_PQ_RPTR_REPORT_ADDR macro
H A Dgc_11_0_0_offset.h4622 #define regCP_HQD_PQ_RPTR_REPORT_ADDR macro