Searched refs:regCP_HQD_PQ_RPTR (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mes_v11_0.c | 1542 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); in mes_v11_0_kiq_dequeue()
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| H A D | mes_v12_0.c | 1720 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); in mes_v12_0_kiq_dequeue_sched()
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| H A D | mes_v12_1.c | 1659 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); in mes_v12_1_kiq_dequeue_sched()
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| H A D | gfx_v12_0.c | 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
3326 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v12_0_kiq_init_register()
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| H A D | gfx_v11_0.c | 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
4468 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
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| H A D | gfx_v12_1.c | 2292 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, in gfx_v12_1_xcc_kiq_init_register()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 3302 #define regCP_HQD_PQ_RPTR … macro
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| H A D | gc_9_4_2_offset.h | 713 #define regCP_HQD_PQ_RPTR … macro
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| H A D | gc_12_0_0_offset.h | 3862 #define regCP_HQD_PQ_RPTR … macro
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| H A D | gc_11_0_3_offset.h | 4844 #define regCP_HQD_PQ_RPTR … macro
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| H A D | gc_11_0_0_offset.h | 4620 #define regCP_HQD_PQ_RPTR … macro
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