| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mes_v11_0.c | 1534 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_queue_init_register()
1537 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_queue_init_register()
1568 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in mes_v11_0_queue_init_register()
1838 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_kiq_dequeue()
1843 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_kiq_dequeue()
1845 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); in mes_v11_0_kiq_dequeue()
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| H A D | mes_v12_1.c | 1387 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v12_1_queue_init_register()
1390 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v12_1_queue_init_register()
1421 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in mes_v12_1_queue_init_register()
1721 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v12_1_kiq_dequeue_sched()
1726 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v12_1_kiq_dequeue_sched()
1728 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); in mes_v12_1_kiq_dequeue_sched()
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| H A D | mes_v12_0.c | 1610 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v12_0_queue_init_register()
1613 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v12_0_queue_init_register()
1644 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in mes_v12_0_queue_init_register()
1925 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v12_0_kiq_dequeue_sched()
1930 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v12_0_kiq_dequeue_sched()
1932 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); in mes_v12_0_kiq_dequeue_sched()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 206 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data); in hqd_load_v11()
854 (RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL) & in get_wave_count()
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| H A D | amdgpu_amdkfd_gfx_v12.c | 415 (RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL) & in get_wave_count()
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| H A D | amdgpu_amdkfd_gfx_v12_1.c | 418 (RREG32_SOC15(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL) & in get_wave_count()
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| H A D | gfx_v9_4_3.c | 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
1794 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1915 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
1984 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
2040 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); in gfx_v9_4_3_xcc_q_fini_register()
2041 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v9_4_3_xcc_q_fini_register()
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| H A D | gfx_v12_1.c | 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
2602 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_1_xcc_kiq_init_register()
2655 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_1_xcc_kiq_init_register()
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| H A D | gfx_v12_0.c | 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
3344 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_0_kiq_init_register()
3405 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v12_0_kiq_init_register()
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| H A D | gfx_v11_0.c | 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
4504 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4565 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 3312 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
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| H A D | gc_9_4_2_offset.h | 723 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
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| H A D | gc_12_0_0_offset.h | 3872 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
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| H A D | gc_11_0_3_offset.h | 4854 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
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| H A D | gc_11_0_0_offset.h | 4630 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
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