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Searched refs:regCP_HQD_PQ_CONTROL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
1892 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
2004 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dmes_v11_0.c1225 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
H A Dmes_v12_0.c1313 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v12_0_queue_init_register()
H A Dgfx_v12_0.c146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
3096 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v12_0_compute_mqd_init()
3221 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
4173 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v11_0_compute_mqd_init()
4299 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v11_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3314 #define regCP_HQD_PQ_CONTROL … macro
H A Dgc_9_4_2_offset.h725 #define regCP_HQD_PQ_CONTROL … macro
H A Dgc_11_5_0_offset.h3605 #define regCP_HQD_PQ_CONTROL … macro
H A Dgc_12_0_0_offset.h3874 #define regCP_HQD_PQ_CONTROL … macro
H A Dgc_11_0_3_offset.h4856 #define regCP_HQD_PQ_CONTROL … macro
H A Dgc_11_0_0_offset.h4632 #define regCP_HQD_PQ_CONTROL … macro