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Searched refs:regCP_HQD_IQ_TIMER_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3325 #define regCP_HQD_IQ_TIMER_BASE_IDX … macro
H A Dgc_9_4_2_offset.h736 #define regCP_HQD_IQ_TIMER_BASE_IDX … macro
H A Dgc_12_0_0_offset.h3885 #define regCP_HQD_IQ_TIMER_BASE_IDX … macro
H A Dgc_11_0_3_offset.h4867 #define regCP_HQD_IQ_TIMER_BASE_IDX … macro
H A Dgc_11_0_0_offset.h4643 #define regCP_HQD_IQ_TIMER_BASE_IDX … macro