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Searched refs:regCP_HQD_GFX_CONTROL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v12_0.c861 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); in mes_v12_0_init_aggregated_doorbell()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3268 #define regCP_HQD_GFX_CONTROL … macro
H A Dgc_9_4_2_offset.h679 #define regCP_HQD_GFX_CONTROL … macro
H A Dgc_12_0_0_offset.h3732 #define regCP_HQD_GFX_CONTROL … macro
H A Dgc_11_0_3_offset.h4676 #define regCP_HQD_GFX_CONTROL … macro
H A Dgc_11_0_0_offset.h4452 #define regCP_HQD_GFX_CONTROL … macro