Searched refs:regCP_HQD_EOP_CONTROL (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v12_0.c | 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
3309 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v12_0_kiq_init_register()
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| H A D | gfx_v11_0.c | 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
4451 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v11_0_kiq_init_register()
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| H A D | gfx_v12_1.c | 2275 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, in gfx_v12_1_xcc_kiq_init_register()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 3364 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_9_4_2_offset.h | 775 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_12_0_0_offset.h | 3922 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_11_0_3_offset.h | 4906 #define regCP_HQD_EOP_CONTROL … macro
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| H A D | gc_11_0_0_offset.h | 4682 #define regCP_HQD_EOP_CONTROL … macro
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