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Searched refs:regCP_HQD_EOP_CONTROL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
3269 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v12_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3364 #define regCP_HQD_EOP_CONTROL … macro
H A Dgc_9_4_2_offset.h775 #define regCP_HQD_EOP_CONTROL … macro
H A Dgc_12_0_0_offset.h3922 #define regCP_HQD_EOP_CONTROL … macro
H A Dgc_11_0_3_offset.h4906 #define regCP_HQD_EOP_CONTROL … macro
H A Dgc_11_0_0_offset.h4682 #define regCP_HQD_EOP_CONTROL … macro