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Searched refs:regCP_HQD_CNTL_STACK_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3378 #define regCP_HQD_CNTL_STACK_OFFSET … macro
H A Dgc_9_4_2_offset.h789 #define regCP_HQD_CNTL_STACK_OFFSET … macro
H A Dgc_11_5_0_offset.h3669 #define regCP_HQD_CNTL_STACK_OFFSET … macro
H A Dgc_12_0_0_offset.h3936 #define regCP_HQD_CNTL_STACK_OFFSET … macro
H A Dgc_11_0_3_offset.h4920 #define regCP_HQD_CNTL_STACK_OFFSET … macro
H A Dgc_11_0_0_offset.h4696 #define regCP_HQD_CNTL_STACK_OFFSET … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
H A Dgfx_v12_0.c161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
H A Dgfx_v11_0.c201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),