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Searched refs:regCP_HQD_ACTIVE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c254 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data); in hqd_load_v11()
457 act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_is_occupied_v11()
519 temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_destroy_v11()
H A Dmes_v11_0.c446 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_reset_queue_mmio()
1270 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v11_0_queue_init_register()
1523 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v11_0_kiq_dequeue()
1526 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_kiq_dequeue()
H A Dmes_v12_0.c469 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_reset_queue_mmio()
1435 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v12_0_queue_init_register()
1701 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v12_0_kiq_dequeue_sched()
1704 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_kiq_dequeue_sched()
H A Damdgpu_amdkfd_gc_9_4_3.c355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
H A Dgfx_v12_0.c3257 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v12_0_kiq_init_register()
3277 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v12_0_kiq_init_register()
3280 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v12_0_kiq_init_register()
3350 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v12_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3286 #define regCP_HQD_ACTIVE … macro
H A Dgc_9_4_2_offset.h697 #define regCP_HQD_ACTIVE … macro
H A Dgc_12_0_0_offset.h3846 #define regCP_HQD_ACTIVE … macro
H A Dgc_11_0_3_offset.h4828 #define regCP_HQD_ACTIVE … macro
H A Dgc_11_0_0_offset.h4604 #define regCP_HQD_ACTIVE … macro