| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v11.c | 255 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data); in hqd_load_v11()
458 act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_is_occupied_v11()
520 temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_destroy_v11()
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| H A D | mes_v11_0.c | 482 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in mes_v11_0_clear_hqds_on_mec_pipe()
684 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_reset_queue_mmio()
1575 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v11_0_queue_init_register()
1830 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v11_0_kiq_dequeue()
1833 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_kiq_dequeue()
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| H A D | mes_v12_0.c | 498 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in mes_v12_0_clear_hqds_on_mec_pipe()
639 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_reset_queue_mmio()
1651 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v12_0_queue_init_register()
1917 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v12_0_kiq_dequeue_sched()
1920 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_kiq_dequeue_sched()
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| H A D | gfx_v9_4_3.c | 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE),
307 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_kiq_reset_hw_queue()
1919 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v9_4_3_xcc_kiq_init_register()
1922 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_xcc_kiq_init_register()
2000 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, in gfx_v9_4_3_xcc_kiq_init_register()
2016 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v9_4_3_xcc_q_fini_register()
2021 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_xcc_q_fini_register()
2030 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); in gfx_v9_4_3_xcc_q_fini_register()
3583 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v9_4_3_unmap_done()
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| H A D | mes_v12_1.c | 1428 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v12_1_queue_init_register()
1713 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in mes_v12_1_kiq_dequeue_sched()
1716 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in mes_v12_1_kiq_dequeue_sched()
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| H A D | gfx_v12_1.c | 2586 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); in gfx_v12_1_xcc_kiq_init_register()
2606 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v12_1_xcc_kiq_init_register()
2609 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v12_1_xcc_kiq_init_register()
2671 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, in gfx_v12_1_xcc_kiq_init_register()
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| H A D | gfx_v12_0.c | 3330 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v12_0_kiq_init_register()
3350 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v12_0_kiq_init_register()
3353 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v12_0_kiq_init_register()
3423 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v12_0_kiq_init_register()
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| H A D | gfx_v11_0.c | 4490 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
4510 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
4513 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
4583 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
5230 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 3286 #define regCP_HQD_ACTIVE … macro
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| H A D | gc_9_4_2_offset.h | 697 #define regCP_HQD_ACTIVE … macro
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| H A D | gc_12_0_0_offset.h | 3846 #define regCP_HQD_ACTIVE … macro
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| H A D | gc_11_0_3_offset.h | 4828 #define regCP_HQD_ACTIVE … macro
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| H A D | gc_11_0_0_offset.h | 4604 #define regCP_HQD_ACTIVE … macro
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