| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v11.c | 254 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data); in hqd_load_v11()
457 act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_is_occupied_v11()
519 temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_destroy_v11()
|
| H A D | mes_v11_0.c | 446 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_reset_queue_mmio()
1270 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v11_0_queue_init_register()
1523 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v11_0_kiq_dequeue()
1526 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_kiq_dequeue()
|
| H A D | mes_v12_0.c | 469 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_reset_queue_mmio()
1435 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v12_0_queue_init_register()
1701 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v12_0_kiq_dequeue_sched()
1704 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v12_0_kiq_dequeue_sched()
|
| H A D | amdgpu_amdkfd_gc_9_4_3.c | 355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
|
| H A D | mes_v12_1.c | 1343 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v12_1_queue_init_register()
1640 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in mes_v12_1_kiq_dequeue_sched()
1643 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in mes_v12_1_kiq_dequeue_sched()
|
| H A D | gfx_v12_1.c | 2263 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); in gfx_v12_1_xcc_kiq_init_register()
2283 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { in gfx_v12_1_xcc_kiq_init_register()
2286 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) in gfx_v12_1_xcc_kiq_init_register()
2348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, in gfx_v12_1_xcc_kiq_init_register()
|
| H A D | gfx_v12_0.c | 3297 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v12_0_kiq_init_register()
3317 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v12_0_kiq_init_register()
3320 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v12_0_kiq_init_register()
3390 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v12_0_kiq_init_register()
|
| H A D | gfx_v11_0.c | 4439 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
4459 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
4462 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
4532 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
5126 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 3286 #define regCP_HQD_ACTIVE … macro
|
| H A D | gc_9_4_2_offset.h | 697 #define regCP_HQD_ACTIVE … macro
|
| H A D | gc_12_0_0_offset.h | 3846 #define regCP_HQD_ACTIVE … macro
|
| H A D | gc_11_0_3_offset.h | 4828 #define regCP_HQD_ACTIVE … macro
|
| H A D | gc_11_0_0_offset.h | 4604 #define regCP_HQD_ACTIVE … macro
|