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Searched refs:regCP_GFX_RS64_DC_BASE_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2787 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2790 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2910 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2913 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
3402 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3405 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3621 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3624 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
H A Dgfx_v12_0.c2502 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2505 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2647 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2650 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h5184 #define regCP_GFX_RS64_DC_BASE_CNTL … macro
H A Dgc_11_0_3_offset.h8298 #define regCP_GFX_RS64_DC_BASE_CNTL … macro
H A Dgc_11_0_0_offset.h7994 #define regCP_GFX_RS64_DC_BASE_CNTL … macro