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Searched refs:regCP_GFX_MQD_CONTROL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3122 #define regCP_GFX_MQD_CONTROL … macro
H A Dgc_9_4_2_offset.h655 #define regCP_GFX_MQD_CONTROL … macro
H A Dgc_11_5_0_offset.h3423 #define regCP_GFX_MQD_CONTROL … macro
H A Dgc_12_0_0_offset.h3730 #define regCP_GFX_MQD_CONTROL … macro
H A Dgc_11_0_3_offset.h4674 #define regCP_GFX_MQD_CONTROL … macro
H A Dgc_11_0_0_offset.h4450 #define regCP_GFX_MQD_CONTROL … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c2850 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); in gfx_v12_0_gfx_mqd_init()
H A Dgfx_v11_0.c3921 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); in gfx_v11_0_gfx_init_queue()